The present invention relates to a protection circuit for providing ESD (electrostatic discharge) protection for integrated circuits.
ESD is a common problem in any monolithic IC circuit, such as CMOS, BICMOS, and bipolar. Static charges can build up high voltages which when discharged through the leads of integrated circuits can cause catastrophic failure. In the prior art, it was known, for example, to protect CMOS circuits by using an input resistor followed by a diode to the V.sub.dd power rail and a diode to the V.sub.ss power rail for each input pad. The separate diode to V.sub.ss was used for each input to protect it against ESD discharges between that input and V.sub.ss.
The problem with this arrangement is that the diodes to V.sub.ss are placed at each input pad and consume significant die area, thereby incurring a significant cost penalty. Furthermore, the V.sub.ss diodes are close to active circuitry, and care has to be taken to prevent latch-up problems caused by the protection diodes.